Decreases in the manufacturing yield of semiconductor devices have been considered mainly due to randomly caused defects, such as foreign matter or impurity. The yield has been maintained by searching for relevant factors using a defect inspection device or a defect review device, and then implementing a countermeasure in a manufacturing step. However, in recent years, the minimum pattern line width of semiconductor devices has become smaller from 32 nm to 22 nm and is advancing toward 10× nm with an accompanying increase in the ratio of defects depending on design data.
A defect having design dependency is referred to as a “systematic defect”. The systematic defect includes, for example, resistance abnormality caused by a pattern shape variation due to an underlying height difference, and contact hole conduction failure due to insufficient etching of a gate oxide film in a specific area.
In order to decrease semiconductor wafer defects, inspection is performed during the manufacture of the wafer using various defect inspection devices, such as a dark-field system, a bright-field system, or an electron beam system. Based on defect position information detected by these defect inspection devices, a clear image of a defect is acquired by a review device. Based on the acquired image, the defect is automatically classified by automatic defect classification (ADC), and a defect countermeasure is taken in accordance with the category and frequency of the classified defect.
However, the conventional ADC technology merely classifies the defect into a category according to the shape and brightness and the like of the defect observed in the review device, and is not capable of clarifying the cause of the defect. The cause of a systematic defect in some cases may be analyzed based on the manner in which layers are superposed in a manufacturing step, or the manner in which a plurality of steps is implemented in a specific layer (such as for multiple patterning). Thus, recently, there is a demand for a technology for classifying defects using the design data for each step.
Conventionally, there have already been attempts to associate a defect with design data. For example, Patent Literature 1 describes that “using layout design data corresponding to a layer currently formed on a device to be inspected and an upper or lower layer formed on the current layer, the defect classification definition unit 221 defines a defect classification area on the surface of the device to be inspected.” Patent Literature 1 further describes that “the defect classification process unit 222, with regard to sampling defect data 133 (233) sampled from a defect acquired by the defect review device 10, classifies the defect depending on in which area of the defined area the position of the defect is included.”